Matilda Bailey has spent her career dissecting the intricate plumbing of our digital world, specializing in the intersection of high-speed networking and cellular infrastructure. As the edge computing landscape shifts from simple data collection to complex, autonomous decision-making, her insights into how hardware handles real-time demands have become essential for understanding the future of industrial automation. With the recent unveiling of Intel’s latest industrial-grade processors at Embedded World 2026, we sat down with her to discuss the move toward deterministic performance and the tactical trade-offs being made in the quest for a more intelligent, responsive edge.
Our conversation explores the critical role of low-latency communication in robotics and the evolving strategy of using specialized silicon versus platform consolidation. We also dive into the technical hurdles of deploying multimodal AI in healthcare settings, where the stakes of a delayed signal can be life-altering. Throughout the discussion, we examine how new benchmarking tools and architectural shifts are helping manufacturers move away from fragmented software stacks toward more unified, powerful systems that prioritize reliability over raw computational speed.
Reducing maximum PCIe latency by more than four times significantly changes how factory robotics function. How does this improvement affect the coordination of high-speed assembly lines, and what specific advantages does a more deterministic response time provide over using high-performance consumer-grade processors?
In a high-speed assembly environment, we aren’t just looking for raw speed; we are looking for a rhythmic, predictable heartbeat across the entire line. When you reduce maximum PCIe latency by up to 4.4 times, you are effectively removing the “jitter” that causes a robotic arm to hesitate for a fraction of a millisecond, which can be the difference between a perfect weld and a structural failure. Consumer-grade processors are designed for bursty workloads—streaming a video or loading a webpage—where a slight delay is invisible to the user, but in a factory, that inconsistency creates chaos. By achieving up to 3.8 times improved deterministic performance, these new industrial platforms ensure that the handoff between sensors and actuators happens in a fixed window of time. This precision allows operators to crank up the line speed without fearing that the control system will fall out of sync, providing a level of reliability that consumer chips, which lack these specific real-time extensions, simply cannot guarantee.
Moving toward a hardware strategy that uses separate chips for deterministic control and AI inference involves unique challenges. How do you balance the desire to consolidate workloads on one platform with the need for specialized silicon, and what are the practical implications for managing these different architectures?
There is a fascinating tension right now between the “two-chip story”—using something like the Core Series 2 for control and the Core Ultra Series 3 for AI—and the industry’s hunger for total consolidation. From a management perspective, maintaining two different silicon architectures can be a headache for IT teams because it often means managing two different driver sets, thermal profiles, and software update cycles. However, the specialized approach exists because AI inference is notoriously resource-hungry and can “steal” cycles from the critical control tasks if they aren’t properly isolated. If an AI model suddenly spikes in activity while a robot is mid-motion, you cannot afford for that control loop to wait; that is why we see this push for deterministic P-cores that handle the heavy lifting of multi-threaded performance, which is up to 1.5 times higher than previous generations. Ultimately, the goal is to reach a point where the software layers are unified enough that the underlying hardware complexity is invisible to the developer, even if the silicon itself remains specialized.
Healthcare environments are now integrating multimodal AI for tasks like arrhythmia detection and 3D patient tracking. What technical hurdles do developers face when moving these workloads from a laboratory setting to a local device, and how do real-world benchmarking tools assist in that transition?
The move from the lab to the bedside is a transition from a sanitized environment with infinite resources to a chaotic, high-pressure setting where every watt of power and every byte of memory counts. When you are running multimodal AI—combining ECG data with 3D visual tracking—the primary hurdle is ensuring that the local hardware can process these disparate data streams simultaneously without overheating or lagging. Real-world benchmarking tools are vital here because synthetic tests often fail to capture the “messiness” of clinical data, such as a patient moving unexpectedly or a sensor signal being interrupted. These suites allow developers to test reference pipelines for things like remote photoplethysmography under actual load, ensuring the system remains stable even when monitoring multiple patients at once. It’s about moving past the “peak performance” marketing numbers and proving that a device can sustain 24/7 operation in a cramped, unventilated hospital equipment closet.
In mission-critical sectors, predictable timing is often more important than raw AI speed. Why is this trade-off necessary for the safety of medical and industrial systems, and what steps should engineers take to ensure that latency-sensitive tasks remain reliable even during heavy computational bursts?
In a mission-critical scenario, a late answer is often as dangerous as a wrong answer, which is why we prioritize a 2.5 times better deterministic response time over just having the fastest clock speed. Imagine an automated surgical assistant or a high-speed sorter; if the AI identifies a problem but the system takes too long to signal the mechanical “stop,” the window for safety has already closed. Engineers need to implement strict hardware-level partitioning, ensuring that the performance cores (P-cores) are dedicated to the “hard” real-time tasks while the AI accelerators handle the “soft” tasks in the background. By using platforms that explicitly narrow the gap with specialized microcontrollers, engineers can build in a safety buffer that prevents a heavy computational burst from “bleeding” into the control loop. This requires a shift in mindset: instead of asking “how fast can this go?”, we must ask “how consistently can this perform under the worst possible conditions?”
Many organizations are shifting away from specialized microcontrollers toward architectures that offer broader software compatibility. How does this transition impact long-term development costs for original equipment manufacturers, and what strategies help maintain system stability when consolidating legacy software onto newer, more powerful edge platforms?
The move away from proprietary microcontrollers toward more compatible x86-based architectures is a massive win for reducing long-term development costs, primarily because it stops the fragmentation of the software stack. When an OEM can use the same code base from the cloud down to the industrial gateway, they save thousands of man-hours that would otherwise be spent on “porting” software between different chip architectures like ARM or specialized DSPs. To maintain stability during this consolidation, the best strategy is to leverage virtualization and real-time containers that allow legacy software to run in an isolated “bubble” while the newer AI workloads run alongside it. This prevents the “noisy neighbor” effect, where a modern, data-heavy AI application might inadvertently starve an older, mission-critical control program of the resources it needs. It allows companies to modernize their hardware without having to rewrite thirty years of proven, reliable control logic from scratch.
What is your forecast for the adoption of real-time AI at the edge in industrial and healthcare settings?
I expect we will see an aggressive acceleration of real-time AI adoption through 2026, specifically as the industry moves past the “experimental” phase and into standardized deployment. The pressure of staffing shortages in healthcare and the need for hyper-efficiency in manufacturing will drive a 50% increase in the deployment of integrated AI nodes that can handle both deterministic control and complex inference. We will likely move away from “all-purpose” edge servers toward highly tuned, discrete devices that are smaller, use less power, and are specifically certified for mission-critical reliability. The real winners in this space won’t be the ones with the highest TFLOPS, but the ones who can guarantee that their AI will never interfere with the “heartbeat” of the systems they are designed to improve. In the end, the edge will become invisible—a seamless, reliable layer of intelligence that responds to the physical world as quickly as the human nervous system.
